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? semiconductor components industries, llc, 2006 october, 2006 ? rev. 5 1 publication order number: nis5102/d nis5102 high side smart hotplug ic/inrush limiter/circuit breaker the nis5102 is a controller/fet ic that saves design time and reduces the number of components required for a complete hot swap application. it is designed for +12 v applications. this chip includes a time delay for sequencing applications. it has a dual function ovlo pin that allows multiple units to be ganged together for simultaneous turn?on and shutdown, allowing units to be operated in parallel. it allows for user selectable undervoltage and overvoltage lockout levels. its unique current limit circuit allows for adjustable current limit levels with no external power resistor. an internal temperature limiting circuit greatly increases the reliability of this device. features ? integrated power device ? power device thermally protected ? no external current shunt required ? simultaneous shutdown and startup for parallel operation ? enable/timer pin ? power good ? 9.0 to 18 v input range ? 10 m ? main/mirror mosfet current ratio 1000:1 ? pb?free packages are available typical applications ? high availability systems ? electronic circuit breaker ? 12 v distributed architecture x = 1 or 2 a = assembly location wl = wafer lot y = year ww = work week g = pb?free 5102qpxh awlywwg 1 http://onsemi.com 9x9 mm, 12 pin pllp case 488ab marking diagram ?? ? ? ? ? ? ordering information nis5102qp1ht1 (latchoff) 9x9 mm 12 pin pllp 1500/tape & ree l nis5102qp1ht1g (latchoff) 12 pin pllp (pb?free) 1500/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. pin connections 12 11 10 9 8 7 1 2 3 4 5 6 13 (bottom view) NIS5102QP2HT1 (auto?retry) 9x9 mm 12 pin pllp 1500/tape & ree l NIS5102QP2HT1g (auto?retry) 12 pin pllp (pb?free) 1500/tape & ree l
nis5102 http://onsemi.com 2 13 uvlo 2 1 5 source 10, 11, 12 gnd 4 7 3 figure 1. block diagram charge pump current limit voltage regulator thermal shutdown undervoltage lockout power good common shutdown overvoltage shutdown enable/ timer enable/timer c charge v cc power good ovlo current limit 6 pin function description pin function description 1 ovlo the overvoltage shutdown point is programmed by a resistor from this pin to the v cc supply. when tied together with other devices, this pin also communicates a shutdown state due to undervoltage and overtemperature reasons. all devices connected will simultaneously shutdown. startup for this condition may be simultaneous or sequenced. 2 uvlo a resistor from v cc to the uvlo pin adjusts the voltage at which the device will turn on. 3 enable/timer a high level signal on this pin allows the device to begin operation. connection of a capacitor will delay turn on for timing purposes. a low input signal inhibits the operation, and communicates to any other paralleled devices (via the ovlo pin) to shutdown. this signal can also be used to reset the thermal latch. 4 ground negative input voltage to the device. this is used as the internal reference for the ic. 5 c charge an external capacitor is required from this pin to the source pin. this is the storage capacitor for the internal charge pump. a small internal capacitor is included for noise filtering. 6 i limit a resistor (r limit ) tied from this pin to the source pin sets the current limit level. 7 power good a high impedance signal on this pin indicates that the power device is conducting. 8, 9 no connection ? 10, 11, 12 source source of power fet, which is also the switching node for the load. 13 v cc positive input voltage to the device.
nis5102 http://onsemi.com 3 maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit input voltage, operating, steady?state (input + to input ?) v in ?0.3 to 18 v input voltage, operating, transient (input + to input ?), 1 second v in ?0.3 to 25 v drain voltage, operating, steady?state (drain to input ?) v dd ?0.3 to 18 v drain voltage, operating, transient (drain to input ?), 1 second v dd ?0.3 to 25 v drain current, peak i dpk 20 a continuous current (t a = 25 c, 0.5 in 2 pad) i davg 10 a voltage on power good pin (pin 7) v max7 20 v thermal resistance, junction?to?air 0.5 in 2 copper 1 in 2 copper q ja 76.5 41.2 c/w c/w thermal resistance, junction?to?lead q jl 3.2 c/w power dissipation (t a = 25 c, 0.5 in 2 pad) p max 1.4 w operating temperature range (note 1) t j ?40 to 175 c non?operating temperature range t j ?55 to 175 c lead temperature, soldering (10 sec) t l 235 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temp erature as specified. electrical characteristics (v cc = 12 v, r limit = 36 , c charge = 100 pf, t j = 25 c unless otherwise noted.) characteristic symbol min typ max unit power fet delay time (enable high to i s = 100 ma) t dly ? 2.0 ? ms charging time (i s = 100 ma to i s = 5.0 a, r limit = 36 ) t chg ? 1.0 ? ms on resistance (v cc = 12 v, i s = 5.0 a) (note 2) r dson ? 10 13 m zero gate voltage drain current (v ds = 12 v dc , v gs = 0 v dc ) i dss1 ? ? 10 a zero gate voltage drain current (v ds = 18 v dc , v gs = 0 v dc ) i dss2 ? ? 100 a output capacitance (v ds = 12 v dc , v gs = 0 v dc , f = 10 khz) ? ? ? ? pf thermal limit shutdown temperature (note 3) t sd 125 135 145 c hysteresis (note 3) t hyst ? 40 ? c over/undervoltage uvlo turn?on (input + increasing, rext uvlo = 620 k) v on 10.05 11.15 12.30 v uvlo hysteresis (input + decreasing, rext uvlo = 620 k) v hyst 0.45 0.62 0.75 v ovlo turn?off (input + increasing, rext uvlo = 620 k) v off 14.0 16.4 19.0 v ovlo hysteresis (input + decreasing, rext uvlo = 620 k) v hyst 0.6 0.78 1.0 v parallel shutdown (alternate function on ovlo pin) device fan?out (minimum external resistor value = 2.0 k (note 3) n fan ? ? 4.0 devices shutdown voltage threshold (ovlo pin) v sd 0.6 0.8 ? v shutdown state output voltage (isink = 2.0 ma) v low ? 0.3 0.4 v 2. pulse test: pulse width 300 s, duty cycle 2%. 3. verified by design.
nis5102 http://onsemi.com 4 electrical characteristics (continued) (v cc = 12 v, r limit = 36 , c charge = 100 pf, t j = 25 c unless otherwise noted.) characteristic symbol min typ max unit current limit current limit (short circuit, r limit = 36 ) i lim1 3.8 4.8 5.8 a current limit (overload, r limit = 36 ) (note 3) i lim2 7.0 7.8 8.6 a enable/timer enable voltage (turn?on) v enon 2.2 ? ? v enable voltage (turn?off) v enoff ? ? 1.6 v charging current (into external capacitor) i charge 65 77 88 a turn?on delay (time from enable high to i source = 100 ma) t delay ? 2.2 ? ms charge pump c charge (voltage on pin 5 with respect to ground) v cc = 18 vdc v ccharge ? ? 18 26 ? ? v v power good power good high z signal when fet is fully enhanced ? ? ? ? ? low z state output voltage (i sink = 2 ma) vpin7 ? 230 300 mv leakage current (vpin7 = 12 v, high z state) i leak ? 2.0 10 a power good delay (time from power fet is fully enhanced to power good fet changing state) t pwrgood ? 15 ? ms total device bias current (operational, v cc = 12 v) i bias ? 1.3 2.0 ma bias current (non?operational, v cc = 7 v)) i bias ? 400 700 a minimum operating voltage vcc min ? 8.5 9.0 v enable/timer input threshold source voltage output current figure 2. timing diagram for external enabled delay
nis5102 http://onsemi.com 5 0.1 1 10 100 10 100 1000 100 200 300 400 500 600 700 800 900 100 0 uvlo trip point (v) figure 3. uvlo adjustment figure 4. ovlo adjustment r uvlo (k ) 19 figure 5. current limit adjustment overload i limit (a) r ilmit ( ) 8 9 10 11 12 13 14 1000 500 900 turn?on turn?off 18 17 16 15 14 13 12 11 10 9 ovlo trip point (v) r ovlo (k ) turn?on turn?off short circuit 200 300 400 600 700 800 0.01 0.1 1 10 10 100 1000 0 figure 6. load capacitance vs. output di/dt di/dt (a/ms) load capacitance ( f) vin = 12 v rext_ilimit = 100 1000 figure 7. continuous current vs. case temperature (test performed on a double?sided copper board, 1 oz) 105 95 85 75 65 55 45 35 25 13 11 9.0 7.0 5.0 3.0 1.0 continuous current, a case temperature, c 1/4 sq in copper area 1 sq in copper area 2 sq in copper area typical performance curves (t a = 25 c unless otherwise noted) device reaching thermal shutdown r ds(on) , (m ) figure 8. typical r ds(on) vs. junction temperature t j , junction temperature, ( c) 4 6 8 10 12 14 16 12 5 565 ?40 ?25 ?10 20 35 50 110 80 95 0 2
nis5102 http://onsemi.com 6 typical application circuits and operation waveforms (t a = 25 c unless otherwise noted) + gnd en/timer vcc ovlo uvlo power good source figure 9. typical applications circuit + c c charge r uvlo r ovlo c delay dc?dc converter figure 10. turn?on waveforms for 3300 f load capacitors figure 11. turn?on waveforms for shorted output, latchoff device c charge current limit r limit input voltage gnd output current output voltage power good power good delay turn on delay input voltage input voltage output current output voltage device reaching thermal limit
nis5102 http://onsemi.com 7 typical application circuits and operation waveforms (continued) (t a = 25 c unless otherwise noted) input voltage output current output voltage device reaching thermal limit power good input voltage output current output voltage device reaching thermal limit power good input voltage output current overvoltage condition output voltage power good input voltage output current overvoltage condition output voltage power good figure 12. turn?on waveforms for shorted output, auto?retry device figure 13. device response during an overvoltage condition
nis5102 http://onsemi.com 8 + gnd en/timer vcc ovlo uvlo power good source + + c charge r uvlo r ovlo c delay2 dc?dc converter dc?dc converter c charge c delay1 figure 14. turn?on sequencing using power good signal r uvlo r ovlo + + gnd vcc ovlo uvlo power good c charge en/timer c charge r ovlo r uvlo dc?dc converter figure 15. parallel operation / simultaneous turn?on and shutdown current limit r limit gnd en/timer vcc ovlo uvlo power good source c charge current limit r limit c delay source current limit r limit gnd vcc ovlo uvlo power good en/timer c charge source current limit r limit r uvlo c charge figure 16. turn?on waveforms for parallel operation input voltage output voltage i out , device1 i out , device2
nis5102 http://onsemi.com 9 operating description operation the nis5102 has a variety of shutdown and protection features that make this part extremely versatile as well as rugged. for the unit to operate, the input voltage must be within the operating range of the part which is set by the uvlo and ovlo bias resistors. the enable must also be high for operation. current and thermal limit circuits constantly monitor the operation and will protect the unit if either of these parameters exceeds its preset limit. an additional shutdown method, is the use of the ovlo pin, which can be tied in parallel. this allows multiple units to be either operated in parallel, and will shutdown and turn on simultaneously for any fault other than an overvoltage, or it allows these hot plug devices to control independent loads, and shutdown and turn on simultaneously. faults once the load capacitance is charged, the sensefet will become fully enhanced as long as the current does not reach the current limit threshold, or is shutdown due to an overvoltage, undervoltage or thermal fault. both the uvlo and ovlo circuits incorporate hysteresis to assure clean turn?on and turn?offs with no chatter . the thermal latching circuit will require the input power to be recycled to resume operation after a fault. the current limit is always active, so any transient or overload will always be limited. circuit description enable/timer the enable/timer pin can function either as a direct enable pin, or as a time delay. in the enable mode, an open collector device is connected to this pin. when the device is in its low impedance mode, this pin is low and the operation of the chip is disabled. if a time delay is required, a capacitor is added to this pin. figure 17 shows the equivalent circuit for the enable. figure 17. enable/timer circuit enable/ timer 80 a ? + 2.2 v enabled nis5102 if a capacitor is added without an open collector device, the turn on will be delayed from the time at which the uvlo voltage is reached. if an open collector device is also used, the delay will start from the time that it goes into its high impedance state. the capacitor is charged by an internal current source. there is an inherent delay in the turn on of the hot plug device, due to the method of gate drive used. the gate of the power fet is charged through a high impedance resistor, and from the time that the gate starts charging until the time that it reaches its threshold voltage, there will be no conduction. once the gate reaches its threshold voltage, the output current will begin a controlled ramp up phase. this delay will be added to any timing delay due to the enable/timer circuit. power good the power good circuit monitors the v gs voltage of the power sensefet and compares it with the output voltage of the internal charge pump. once the v gs of the power sensefet reaches around 90% of the internal charge pump output voltage, the power good will change its state from low impedance to high impedance but only after the power good delay has elapsed. figure 10 shows the power good behavior during the startup of the nis5102 device, an external pullup resistor from power good to v cc was used. the power good will change its state from high impedance to low impedance in the event of any fault condition such as short circuit and overvoltage. undervoltage lockout the uvlo circuit holds the chip off when the input voltage is less than the turn?on limit. it includes internal hysteresis to assure clean on/off switching. an internal divider sets the turn?on voltage level at 16 v. this voltage can be reduced by adding an external resistor from the uvlo pin to the v cc pin. the equivalent circuit is shown in figure 18.
nis5102 http://onsemi.com 10 v cc r uvlo 400 k uvlo v gs(th) = 1.15 v 40 k 3 k ground source figure 18. equivalent undervoltage lockout circuit the theoretical equation for the uvlo turn?on voltage is: r uvlo (k ) 400 v in 460 17.5 v in the uvlo trip point voltage calculated through the theoretical formula may show small variations with respect to figure 3, therefore it is recommended to use the formulas gotten from the uvlo characterization, which are shown below: r uvlo (k ) e [(uvlo 14.647) 3.9858] ; for t j 25 c where ?uvlo? is the desired undervoltage lockout value, and r uvlo is the programming resistor from the uvlo pin to the v cc pin. to reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the uvlo pin to ground. this will create a low pass filter with a cutoff frequency of f. the required capacitance on this pin is: c uvlo 1 2 f 43 k r uvlo 400 k r uvlo 400 k overvoltage lockout and parallel shutdown the overvoltage lockout (ovlo) is a dual function pin. this pin will normally be biased somewhere between ground and the input voltage, due to an internal voltage divider which sets the turn?off voltage level at 22 v. this voltage level can be reduced by adding an external resistor from the ovlo pin to the v cc pin. when the input voltage reaches the programmed trip point, operation of the device is inhibited. figure 19 shows the equivalent circuit.
nis5102 http://onsemi.com 11 v cc r ovlo 300 k ovlo 200 k ground source figure 19. equivalent overvoltage lockout circuit 2 m 7 v the theoretical equation for the ovlo turn?on voltage is: r ovlo (k ) 300 v in 2100 21.8 v in the ovlo trip point voltage calculated through the theoretical formula may show small variations with respect to figure 4, therefore it is recommended to use the formulas gotten from the ovlo characterization, which are shown below: r ovlo (k ) e [(ovlo 5.2) 3.46] ; for t j 25 c where ?ovlo? is the desired overvoltage lockout value, and r ovlo is the programming resistor from the ovlo pin to the v cc pin. to reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the ovlo pin to ground. this will create a low pass filter with a cutoff frequency of f. the required capacitance on this pin is: c ovlo [1 (8.83 e ?6 r ovlo )] 2 fr ovlo this pin is also used as a common shutdown pin. in this mode, if this pin is pulled to ground, it will shutdown the chip and all chips connected to its ovlo pin. the ovlo pin has an internal switch to ground that will pull it low, whenever the device is disabled due to any fault other than an overvoltage condition. an enable pin shutdown is not considered a fault and will not cause a common shutdown. this feature allows multiple units to turn on and off simultaneously by tying the ovlo pins together in parallel. this can be used for operating several hot plug devices in parallel, or for use with separate loads, when all devices need to startup and shutdown simultaneously. temperature limit the temperature limit circuit senses the temperature of the power fet and removes the gate drive if the maximum level is exceeded. for the auto?retry device, there is a nominal hysteresis of 40 c for this circuit. after a thermal shutdown, the device will automatically restart when the temperature drops to a safe level as determined by the hysteresis. the latching thermal circuit can be reset either by recycling the input power, or by toggling the enable signal. current limit an external resistor from the current limit pin to the source pins set the level at which the device will limit the current. the plot of resistance vs. current limit includes two curves, one for short circuit and one for overload. a short circuit condition is one in which the sensefet is not fully enhanced, and is therefore in a high impedance mode of operation. in this case there are many hundreds of millivolts across the drain to source pins of the sensefet. this occurs when the output sees a very low impedance short as well as when the capacitor is charging at turn on. in both cases there are several volts or more across the fet. an overload condition is one in which the sensefet is still fully enhanced and the drain to source voltage is the product of the drain current and the on resistance of the fet. the sense voltage out of the sensefet has a different relation to the drain current in these two conditions. the difference in current limit levels for these two cases is called di, where: i v ref r dson
nis5102 http://onsemi.com 12 for this equation, v ref is the reference voltage of the current limit circuit, and r dson is the on resistance of the sensefet. for more information on this, see application note and8140/d, ?smart hotplug current limit function?. this inherent property of the sensefet allows for simple dual level current limiting, in which a short circuit condition will see a lower level of limiting than will an overload. this operation will exist in start up as well as under normal operation, so the device will be able to differentiate between a short and an overload. as with all smart hotplug devices, the current limit will never shutdown the device. only the thermal limit will stop the flow of current to the load. once the current is stopped due to the thermal limit, it will remain off until input power is recycled for the latching version, or it will continuously retry to start again if it is the auto?retry version. the ilimit graph shown in figure 5 was generated from the data of the ilimit characterization, the formula for the short circuit curve is: r ilimit ( ) 152.86 ilimit 1.02 for t j 25 c where ?ilimit? is the desired short circuit ilimit value, and r ilimit is the programming resistor from the ilimit pin to the source pin. turn?on surge during the turn?on event, there is a large amount of energy dissipated due to the linear operation of the power device. the energy rating is the amount of energy that the device can absorb before the thermal limit circuit will shut the unit down. this is very important specially for the latch off device as it determines the maximum load capacitance that the device can charge before the thermal limit shuts the device down. the calculation of this is not very simple as it depends on several factors such as the input voltage (vin), load capacitance (cl), current limit settings (ilimit) and device?s thermal transient response, therefore, it is recommended to do lab evaluations for these purposes. figure 20 shows the device?s thermal transient response for minimum pad. 0.1 1 10 100 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (seconds) theta j(t) ( c/w) figure 20. thermal transient response 1?in pad min pad
nis5102 http://onsemi.com 13 package dimensions pllp?12, 9x9 mm case 488ab?01 issue c soldering footprint* 9.305 12 x 5.652 1.054 12 x 0.551 7.652 1.270 pitch dimensions in mm *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. style 1: pin 1. ovlo 2. uvlo 3. enable/timer 4. gnd 5. ccharge 6. current limit 7. power good 8. n/c 9. n/c 10. source 11. source 12. source dim min max millimeters a 1.750 1.950 a1 0.000 0.050 a3 0.254 ref b 0.400 0.600 d 9.000 bsc e 9.000 bsc e 1.270 bsc d2 5.400 5.600 e2 7.400 7.600 k 0.850 ref l 0.850 0.950 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. coplanarity applies to the lead, dimension b, and exposed pad. d e b a 4 x pin one seating location 0.08 c 0.15 c ? ? ? ? ? ? ? d2 e2 b k 12 x l 12 x 10 x e e/2 12 x a m 0.10 b c m 0.05 c top view bottom view side view (a3) a1 a c 0.10 c plane
nis5102 http://onsemi.com 14 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 nis5102/d the product described herein (nis5102), may be covered by one or more of the following u.s. patents: 6,781,502; 6,865,063; 7,09 9,135. there may be other patents pending. smart hotplug and sensefet are trademarks of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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